The manufacture of large scale integrated circuits in a mass production facility involves hundreds of discrete processing steps beginning with the introduction of blank semiconductor wafers at one end and recovering the completed chips at the other. The manufacturing process is usually conceived as consisting of the segment wherein the semiconductor devices are formed within the silicon surface and the portion which includes the formation of the various layers of interconnection metallurgy above the silicon surface. Most of these processing steps involve depositing layers of material, patterning them by photolithographic techniques, and etching away the unwanted portions. The materials consist primarily of insulators and metal alloys. In some instances the patterned layers serve as temporary protective masks. In others they are the functional components of the integrated circuit chip.
Radio-frequency (RF) plasmas may be used extensively in many of these processing steps. Reactive-ion-etching (RIE) provides the etching anisotropy required to achieve a high degree of pattern definition and precise dimensional control. Here the gaseous chemical etching is assisted by unidirectional ion bombardment provided by an RF plasma. Plasma etching, which is accomplished at higher pressures, is isotropic. Photoresist layers too, are frequently removed, not by chemical solvents, but more cleanly by plasma ashing.
A metal-oxide-silicon-field-effect-transistor (MOSFET) is a device consisting of two shallow regions of one type semiconductor—the source and the drain—separated by a region of another type. The conductivity of the central region (channel) is modulated by applying a voltage to an electrode (gate) which overlies the channel region and is separated from it by a thin insulating layer (gate oxide). CMOS (complementary MOS) technology utilizes MOSFETS in pairs, one an n-type channel device (NMOS) and the other a p-type channel device (PMOS). The simple nature of these devices and their minimal heat dissipation permits an extraordinary degree of miniaturization and consequently a high density of circuits.
The gate insulating layer which overlies the channel region usually consists of thermally grown silicon oxide and is one of the most critical components of the MOSFET. The insulating film is highly susceptible to damage from external sources during manufacture. A prominent cause of such damage is ion and electron bombardment from plasmas used while forming the various layers. The surfaces of patterned semiconductor wafers located within a plasma reactor present multiple areas of conductors and insulators to the plasma. These produce local non-uniformities in the plasma currents which result in charge build-up on the electrically floating conductor surfaces.
After the gate oxide layer is formed it is covered with a layer of polysilicon within which the gate electrode is defined. The etching of this polysilicon layer may be accomplished by reactive-ion-etching, providing the first in a series of exposures of the gate oxide to an RF plasma. In this instance, the area of the gate electrode is covered with photoresist. As etching proceeds, the exposed polysilicon provides sufficient conduction to prevent local charge build-up. However, as the endpoint is approached, the polysilicon layer breaks up and residual, now isolated, regions of polysilicon surrounding the photoresist protected gate electrode act as an antenna which accumulate positive charge. This results in the development of a positive potential sufficiently high to cause current flow through the gate oxide. These polysilicon halos can present a high antenna-to-thin oxide area ratio causing massive current flow in the oxide. As etching proceeds, the halos of polysilicon disappear and the antenna area is reduced to the thin edges of the gate electrode itself.
The mechanism of current flow though the gate oxide is primarily Fowler-Nordheim (FN) tunneling. FN tunneling occurs at fields in excess of 10 MV/cm. Charge build up on the gate electrode resulting in a gate electrode potential of only 10 volts is therefore sufficient to induce FN tunneling through an oxide layer of 100 Angstroms. Such potentials are easily achieved in conventional plasma reactors. Excessive FN tunneling currents eventually lead to positively charged interface traps in the oxide and subsequent dielectric breakdown.
A consequence of these numerous exposures of semiconductor wafers to RF plasmas and other forms of ionic radiation, is the potential occurrence of radiation damage and the accumulation of charge on exposed conductive components which leads to damaging current flows and trapped charge affecting the semiconductor devices. Thus, plasma induced damage is a well-known issue during the semiconductor wafer manufacturing process. Sometime referred to as the “antenna effect” or “plasma induced gate oxide damage”, plasma induced damage typically refers to the charge accumulation in isolated nodes during the processing of an integrated circuit. Such damage may affect the reliability and performance of the integrated circuit device.
Therefore there is a need for improved methods and devices for detecting plasma induced damage occurring semiconductor processing.